Title Page
License
± 1. NUMERATION SYSTEMS
1.1. Numbers and symbols
1.2. Systems of numeration
1.3. Decimal versus binary numeration
1.4. Octal and hexadecimal numeration
1.5. Octal and hexadecimal to decimal conversion
1.6. Conversion from decimal numeration
± 2. BINARY ARITHMETIC
2.1. Numbers versus numeration
2.2. Binary addition
2.3. Negative binary numbers
2.4. Subtraction
2.5. Overflow
2.6. Bit groupings
± 3. LOGIC GATES
3.1. Digital signals and gates
3.2. The NOT gate
3.3. The "buffer" gate
3.4. Multiple-input gates
3.5. TTL NAND and AND gates
3.6. TTL NOR and OR gates
3.7. CMOS gate circuitry
3.8. Special-output gates
3.9. Gate universality
3.10. Logic signal voltage levels
3.11. DIP gate packaging
3.12. Contributors
± 4. SWITCHES
4.1. Switch types
4.2. Switch contact design
4.3. Contact "normal" state and make/break sequence
4.4. Contact "bounce"
± 5. ELECTROMECHANICAL RELAYS
5.1. Relay construction
5.2. Contactors
5.3. Time-delay relays
5.4. Protective relays
5.5. Solid-state relays
± 6. LADDER LOGIC
6.1. "Ladder" diagrams
6.2. Digital logic functions
6.3. Permissive and interlock circuits
6.4. Motor control circuits
6.5. Fail-safe design
6.6. Programmable logic controllers
6.7. Contributors
± 7. BOOLEAN ALGEBRA
7.1. Introduction
7.2. Boolean arithmetic
7.3. Boolean algebraic identities
7.4. Boolean algebraic properties
7.5. Boolean rules for simplification
7.6. Circuit simplification examples
7.7. The Exclusive-OR function
7.8. DeMorgan's Theorems
7.9. Converting truth tables into Boolean expressions
± 8. KARNAUGH MAPPING
8.1. Introduction
8.2. Venn diagrams and sets
8.3. Boolean Relationships on Venn Diagrams
8.4. Making a Venn diagram look like a Karnaugh map
8.5. Karnaugh maps, truth tables, and Boolean expressions
8.6. Logic simplification with Karnaugh maps
8.7. Larger 4-variable Karnaugh maps
8.8. Minterm vs maxterm solution
8.9. Σ (sum) and Π (product) notation
8.10. Don't care cells in the Karnaugh map
8.11. Larger 5 and 6-variable Karnaugh maps
± 9. COMBINATIONAL LOGIC FUNCTIONS
9.1. Introduction
9.2. A Half-Adder
9.3. A Full-Adder
9.4. Decoder
9.5. Encoder
9.6. Demultiplexers
9.7. Multiplexers
9.8. Using multiple combinational circuits
± 10. MULTIVIBRATORS
10.1. Digital logic with feedback
10.2. The S-R latch
10.3. The gated S-R latch
10.4. The D latch
10.5. Edge-triggered latches: Flip-Flops
10.6. The J-K flip-flop
10.7. Asynchronous flip-flop inputs
10.8. Monostable multivibrators
± 11. COUNTERS
11.1. Binary count sequence
11.2. Asynchronous counters
11.3. Synchronous counters
11.4. Counter modulus
± 12. SHIFT REGISTERS
12.1. Introduction
12.2. Serial-in/serial-out shift register
12.3. Parallel-in, serial-out shift register
12.4. Serial-in, parallel-out shift register
12.5. Parallel-in, parallel-out, universal shift register
12.6. Ring counters
± 13. DIGITAL-ANALOG CONVERSION
13.1. Introduction
13.2. The R/2nR DAC
13.3. The R/2R DAC
13.4. Flash ADC
13.5. Digital ramp ADC
13.6. Successive approximation ADC
13.7. Tracking ADC
13.8. Slope (integrating) ADC
13.9. Delta-Sigma (ΔΣ) ADC
13.10. Practical considerations of ADC circuits
± 14. DIGITAL COMMUNICATION
14.1. Introduction
14.2. Networks and busses
14.3. Data flow
14.4. Electrical signal types
14.5. Optical data communication
14.6. Network topology
14.7. Network protocols
14.8. Practical considerations
± 15. DIGITAL STORAGE (MEMORY)
15.1. Why digital?
15.2. Digital memory terms and concepts
15.3. Modern nonmechanical memory
15.4. Historical, nonmechanical memory technologies
15.5. Read-only memory
15.6. Memory with moving parts: "Drives"
± 16. PRINCIPLES OF DIGITAL COMPUTING
16.1. A binary adder
16.2. Look-up tables
16.3. Finite-state machines
16.4. Microprocessors
16.5. Microprocessor programming
Appendix 1. ABOUT THIS BOOK
Appendix 2. CONTRIBUTOR LIST
Appendix 3. DESIGN SCIENCE LICENSE
